Various signal lines in memory frequently need to be biased to achieve a particular condition on the signal lines in order to perform a memory operation. For example, a word line or a bit line may need to be biased to have a particular voltage before a read or a write operation can be performed. In today's memory systems, however, signal lines can be relatively long and relatively close to one another, which may result in an unacceptable propagation delay between when a biasing signal is provided to one end of the signal line and when a target (e.g., desired) condition is achieved along the remainder of the signal line. With reference to the timing diagram 101 in FIG. 1, a biasing voltage V-INPUT may be provided to an input node of a signal line at time T0. If the voltage along the signal line is measured at several measurement nodes as a function of time—with the V-START node being near the beginning of the signal line, the V-END node being at the distal end of the signal line, and the V-MID1 and V-MID2 nodes being between the V-START node and the V-END node the timing diagram 101 in FIG. 1 illustrates that the target condition at the V-END node (e.g., V-END=V-INPUT=VT) is achieved at time T1 only after a delay of D1.
Typically, no operation can be performed until the entire signal line is properly biased, and thus memory operations must wait until every point along the signal line is at the target condition. With increasing storage density—and therefore increasing signal line length—the propagation delay may lead to unacceptable delays in performing operations on the memory cells at increasing operating frequencies and may cause a bottleneck in memory system timing. Therefore, attempts have been made to decrease the time needed to achieve the target condition along signal lines prior to a memory operation.
For example, a biasing signal may be preemphasized for some finite period of time, and then the biasing signal may be reduced to a target voltage for the signal line after that initial period of time. Preemphasizing the biasing signal may speed the propagation of a biasing voltage along the signal line, and may therefore allow memory operations to be performed sooner than would otherwise be the case.
Typically, however, little to no control is exerted on the magnitude and duration of the preemphasis of the biasing signal, which can lead to wasted power and less than optimal results.